DC/HRI APID78 29-Mar-24 11:49:20.747 TAI Port State DCHRI Tables, Hist, Comp Channel 1 I_HR_PORT1_STATE ACTIVE I_HR_TABLE_PARITY_ERROR 0 I_HR_CH1_STAR 0x00 I_HR_PORT2_STATE OFF I_HR_TABLE_ID_PAR_ERR 0x01c I_HR_CH1_PR_STAR 0x00 FSN I_HR_HIST_ENA 1 I_HR_CH1_DSM_STAR 0x09 I_HR_CAM_ACT_ISYS_NUM FUV I_HR_CROP_ENA 1 I_HR_CH1_DSM_CMDR 0x00 I_HR_CAM_EXP_ISYS_NUM FUV I_HR_CROP_TABLE_ID 989 I_HR_CH1_DSM_MODR 0x00 I_HR_CAM_ACT_FRAME_SN 122775000 I_HR_CROP_TBL_LD_COUNT 154 I_HR_CH1_COMICFG 0x00 I_HR_CAM_EXP_FRAME_SN 122775000 I_HR_CROP_TABLE_PNTR 0x00000000 I_HR_CH1_CNTRL1 0x00 HR Buffers I_HR_ROW_SIZE 0x00000110 I_HR_CH1_CNTRL2 0x00 I_HR_BUFFER_1_WORD_CNT 0x0000e6ff I_HR_LUT_ENA 1 I_HR_CH1_COMI_P 0x00000000 I_HR_BUFFER_2_WORD_CNT 0x0000e6ff I_HR_LUT_TABLE_ID 0 Channel 2 I_HR_BUFFER_3_WORD_CNT 0x0000f77f I_HR_LUT_TBL_LD_COUNT 88 I_HR_CH2_STAR 0x00 I_HR_BUFFER_4_WORD_CNT 0x0000f77f I_HR_LUT_TABLE_PNTR 0x00000004 I_HR_CH2_PR_STAR 0x00 I_HR_CAM_FSN_ACT 0x075165d8 I_HR_COMP_ENA 1 I_HR_CH2_DSM_STAR 0x00 I_HR_CAM_FSN_EXP 0x075165d8 I_HR_BIT_COMP_K 2 I_HR_CH2_DSM_CMDR 0x00 I_HR_CAM_BUFFER_2_ACT 0x00241c01 I_HR_BIT_COMP_N 14 I_HR_CH2_DSM_MODR 0x00 I_HR_CAM_BUFFER_2_EXP 0x00241c01 I_HR_BIT_SEL_R 0 I_HR_CH2_COMICFG 0x00 I_HR_CAM_SUB_BUF_ENA 0x0f HR State I_HR_CH2_CNTRL1 0x00 IMPDU Packet Info I_HR_OP_MODE RDCA1 I_HR_CH2_CNTRL2 0x00 I_HR_SEQ_CNTR_SCIENCE_0 0x01db I_HR_DCHRI_BUSY 0 Registers I_HR_SEQ_CNTR_SCIENCE_1 0x0000 I_HR_HSS_PARITY_ERROR 0 I_HR_IM_STATUS_REG 0x00000380 I_HR_SEQ_CNTR_HK 0x1c2a I_HR_INIT_PENDING 0 I_HR_CONTROL_REG 0x00000ff4 I_HR_SEQ_CNTR_TEST 0x0000 I_HR_CONFIG_PENDING 0 I_HR_ISR 0x00000000 I_HR_SSEQ_CNTR_PNTR 000 I_HR_HEADER_ERROR 0 I_HR_DC_PARAM_REG 0x00000e20 I_HR_IM_PDU_CNTR_HI 0x00000000 I_HR_DATA_OVERFLOW 0 I_HR_IMR 0x00000000 I_HR_IM_PDU_CNTR_LOW 0x0f48de05 I_HR_ROUTE_CTRL 0x00 I_HR_FPGA_DIAG_REG 0x0000 I_HR_IM_PDU_ID 0x00000011 I_HR_FPGA_VERSION 0x7404 I_HR_COMI_CS0R 0x00 I_HR_BIT_COMP_REG 0x00000072 I_HR_COMI_ACR 0x00 I_HR_COMP_ID_N e Parent Tlm I_HR_TRS_CTRL_REG 0x00 I_HR_COMP_ID_K 02 I_HR_APID_P 0x307c0305 I_HR_SICR 0x00 I_HR_BIT_ID_R 00 I_HR_FPGA_P 0x74040000 Parent Tlm I_HR_TAP_CODE 00 I_HR_TBL_LD_COUNT_P 0x0000589a I_HR_CH1_REG_P1 0x00000000 I_HR_APIK_SCIENCE 0x300 I_HR_ID_CROP_LUT_P 0x400003dd I_HR_CH1_REG_P2 0x00000900 I_HR_APIK_HK 0x305 I_HR_PORT_STATE 0x00000006 I_HR_CH2_REG_P1 0x00000000 I_HR_APIK_TEST 0x307 I_HR_SEQ_CNTR_P1 0x00001c2a I_HR_CH2_REG_P2 0x00000000 SMCS I_HR_SEQ_CNTR_P2 0x000001db I_HR_SMCS_REG_P1 0x00000000 I_HR_SMCS_ERROR 0 I_HR_SMCS_REG_P2 0x000400c4 I_HR_SMCS_BUSY 0 I_HR_SMCS_REG_P3 0x00000007 I_HR_SMCS_ISR_EXP 0x0004 HR Table Dump Base Address I_HR_SMCS_ISR_ACT 0x00c4 I_FHR_DMP_TBL_ADDR 0x002b2088 I_HR_SMCS_ISR_MASK 0x0007